Processing high-speed digital signals

ABSTRACT

A first transparent latch ( 22 ) receives a first synchronised signal (S 1 ) which changes its logic state synchronously with respect to a clock signal (CLK). A second transparent latch ( 24 ) receives a second synchronised signal (S 2 ) output by the first latch ( 22 ). When the clock signal has a first logic state (H) the first latch ( 22 ) has a non-responsive state and the second latch has a responsive state, and when the clock signal has a second logic state (L) the first latch has the responsive state and the second latch has the non-responsive state.  
     In such circuitry the change in logic state of a third synchronised signal (S 3 ) output by the second latch ( 24 ) is guaranteed to occur in a particular half-cycle of the clock signal, irrespective of process/voltage/temperature (PVT) variations of the circuitry.  
     Other embodiments relate to clock recovery circuitry having N(≧2) rising-edge and falling-edge latches (FIG.  6 ); circulating control pattern verification circuitry (FIG.  12 ); data synchronising circuitry for converting parallel data clocked by a first clock signal into serial data clocked by a second clock signal asynchronous with the first clock signal (FIG.  15 ); and data recovery circuitry for producing an offset clock signal which can be chosen freely to suit a data eye shape of a received serial data stream (FIG.  21 ).

BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The present invention relates to processing high-speed digitalsignals and, in particular but not exclusively, to processing high-speeddigital signals to recover clock and/or data signals from receivedhigh-speed signals.

[0003] 2. Description of the Related Art

[0004] Recovery of a clock signal from a serial data stream requiresthat data is latched (sampled) on both the rising and falling clockedges, the data samples then being processed to produce a recoveredclock signal.

[0005] When the frequency of the recovered clock signal (clockfrequency) is high, bordering on the maximum speed of operation of thecircuit elements making up the clock recovery circuitry, several designproblems arise, as follows.

[0006] Firstly, the clock recovery circuitry will require signals whichchange at certain well-defined moments. It may be necessary to controlthe moment a control signal such as a reset signal changes to anaccuracy of half a clock cycle or less. A standard reset circuit,previously considered for use in such clock recovery circuitry, is madeup of two master-slave latches. With such a previously-considered resetcircuit, however, it is found that at frequencies approaching the limitof the technology, it is not possible to guarantee in which half of theclock cycle a reset signal produced by the reset circuit will switchfrom one logical state to the other. This problem arises as theswitching time of a master-slave latch varies due to manufacturing orprocessing tolerances, voltage margins and temperature variations(so-called PVT variation).

[0007] Secondly, the processing of the above-mentioned data samples isalso problematic at very high clock frequencies. This processing isgenerally performed by one of two different methods. In the firstmethod, the samples are examined during the second half of the clockcycle, and the result of the comparison is itself latched at the end ofthe clock cycle (i.e. the next rising clock edge). In the second method,at the end of the clock cycle (i.e. the next rising clock edge) the datasamples are passed unprocessed from a first set of latches to a secondset of latches. The data sample can then be examined during the nextclock cycle. In this case, both samples are now aligned to the risingclock edge.

[0008] In both of the above methods the data sampled on the fallingclock edge must be transferred from one latch to another latch withinhalf a clock cycle. At frequencies bordering on the limit of thetechnology, this can be very difficult.

[0009] Thirdly, in clock recovery circuitry, it is also sometimesrequired to generate a circulating control sequence (e.g. 0111, 1011,1101, 1110, 0111, . . . ) at the outputs of a control register. Thecontrol-register outputs are used to enable different respectivelatches, for example. In practice, however, the circulating controlsequence may become corrupted, with the result that the enabling of thedifferent latches is no longer performed correctly. For controlregisters having a small number of bits (e.g. four bits or less), thecorrectness of the actual individual control states (e.g. 0111, 1011,etc.) can be detected explicitly and checked. However, as the length ofthe control sequence increases (for example to 8 bits or more), thedetection of the correct control states becomes more difficult. Inparticular, more gates are required to implement the circuitry forchecking the correctness of the control states which inevitably leads toincreased loads on the control-register outputs. At frequenciesapproaching the limit of the technology, such increased loading must beavoided if at all possible.

[0010] Fourthly, high-speed digital signal processing circuitry may alsohave a requirement to convert items of data in one form into items ofdata in another form. For example, it may be required to convert n-bitparallel data (n=8, for example) into a serial bit stream, fortransmission at n times the frequency of the parallel data. Separateclock signals are generally provided for the parallel data and theserial data, the serial clock signal having a frequency of n times thatof the parallel clock signal. A shift register or the like is used tostore the parallel data temporarily before it is shifted out of theregister as a serial bit stream, one bit per serial clock cycle. It istherefore necessary to be able to generate a transfer control signal ata suitable moment during each parallel clock cycle to bring abouttransfer of a new item of parallel data into the shift register. Forexample, if the parallel data is permitted to change at each rising edgeof the parallel clock signal, a previously-considered approach is to usefirst and second series-connected latches, the first latch having theparallel clock signal as its data input and both latches being clockedby the serial clock signal. In this case, for n=8 and assuming that theparallel clock signal has a 50% mark-space ratio, the rising edge ofclock cycle 4 of the serial clock signal coincides with the falling edgeof the parallel clock signal. It is then expected that the first latchchanges state, producing a detection signal, during clock cycle 5 of theserial clock signal as clock cycle 5 is the first cycle in which, at therising edge of the cycle, the parallel clock signal has the low logicstate. At the next serial clock cycle, clock cycle 6, the second latchchanges state producing the transfer control signal, and a new item ofparallel data is then transferred into the shift register from which thedata would be shifted out, one bit per serial clock cycle, as the serialbit stream.

[0011] At very high frequencies approaching the limit of the technology,it is very difficult to control the relative phase of the serial clocksignal with respect to that of the parallel clock signal (i.e. acrossall PVT and layout variations). As a result, the parallel clock may inpractice have its falling edge just before, exactly at, or just afterthe rising edge of the serial clock in clock cycle 4. If it is beforethe rising edge, it is possible that the first latch would produce thedetection signal during clock cycle 4 instead of clock cycle 5. In theworst case, the detection signal could become dynamically unstable, i.e.be produced randomly at either serial clock cycle 4 or 5. This wouldcause items of data to be transferred to the shift register at varyingintervals of 7, 8 or 9 serial clock cycles.

[0012] Fifthly, in previously-considered data recovery circuitry, aclock which is recovered from the incoming serial data stream is used tolatch the serial data stream. However, depending on the shape of thedata eye in the serial data stream it may be desirable to use a clockwhich is offset from the recovered clock to perform the serial datalatching. The simplest method for producing such an offset clock signalwould be to delay the recovery clock signal using a delay element.However, this has inherent disadvantages, and in particular the delay ishard to control across process, voltage and temperature variations.Furthermore, such a delay element is difficult to control from outsidethe clock recovery circuitry and can only impose a delay (rather than anadvance) relative to the recovered clock signal.

BRIEF SUMMARY OF THE INVENTION

[0013] In a first aspect of the present invention signal generatingcircuitry comprises a first clocked element connected for receiving aclock signal and a first synchronised signal which changes its logicstate synchronously with respect to said clock signal. The first clockelement is switchable by the clock signal between a responsive state, inwhich the element is operable in response to the state change in saidfirst synchronised signal to change a logic state of a secondsynchronised signal produced thereby, and a non-responsive state inwhich no state change in the second synchronised signal occurs. A secondclocked element of the circuitry is connected for receiving the clocksignal and the second synchronised signal. The second clocked element isswitchable by the clock signal between a responsive state, in which theelement is operable in response to the state change in said secondsynchronised signal to change a logic state of a third synchronisedsignal produced thereby, and a non-responsive state in which no statechange in the third synchronised signal occurs. When the clock signalhas a first logic state the first clocked element has the non-responsivestate and the second clocked element has the responsive state. When theclock signal has a second logic state the first clocked element has theresponsive state and the second clocked element has said non-responsivestate.

[0014] In such signal generating circuitry the state change in the thirdsynchronised signal is guaranteed always to occur in one part of a clockcycle, irrespective of PVT variations. For example, it is possible toguarantee that the third synchronised signal will always change itslogic state in the first half of the clock cycle. This guarantee ispossible, even when the first synchronised signal cannot be guaranteedto change state in a particular half of a cycle, for example because, athigh frequencies and with PVT variation, a master/slave or full latchelement used to generate the first synchronised signal has a switchingtime which may vary on either side of 50% of the clock period.

[0015] In one embodiment, each of the first and second clocked elementsis a transparent or half latch element, for example a transparentlevel-sensitive latch. Such a transparent or half latch element has ashorter switching time than a master/slave or full latch element sothat, even at very high frequencies, it is still possible to guaranteethat the switching time of the transparent or half latch element will beless than half a clock cycle.

[0016] When a clocked element which produces the first synchronisedsignal switches quickly after a working edge of the clock signal (e.g. arising edge) the state change in the first synchronising signal mayoccur in the first half cycle after the working edge. In this case, thefirst clocked element is in the non-responsive state, however, so thatno change in the second synchronised signal occurs until the second halfcycle after the working edge. In that second half cycle, the secondclocked element is in the non-responsive state, so that no change in thethird synchronised signal occurs until the third half cycle followingthe working edge.

[0017] When, on the other hand, the first synchronised signal does notchange until the second half cycle following the working edge (becausethe switching time of the clocked element producing it is slow), thefirst clocked element is already in the responsive state when the changeoccurs. In this case, the state change in the second synchronised signaloccurs in the second half cycle after the working edge, with the resultthat, as in the fast case, the third synchronised signal changes statein the third half cycle after the working edge.

[0018] In another embodiment the signal generating circuitry furthercomprises a third clocked element connected for receiving the clocksignal and the third synchronised signal. The third clocked element isswitchable by the clock signal between a responsive state, in which theelement is operable in response to the state change in the thirdsynchronised signal to change a logic state of a fourth synchronisedsignal produced thereby, and a non-responsive state in which no statechange in the fourth synchronised signal occurs. The third clockedelement has the responsive state when the clock signal has the secondlogic state and has the non-responsive state when the clock signal hasthe first logic state.

[0019] In this embodiment, it can be guaranteed that the change in thefourth synchronised signal will occur in the fourth half cycle followingthe working edge. The third clocked element is preferably a transparentor half latch element.

[0020] In a second aspect of the present invention clock recoverycircuitry is operable to perform a repeating series of N cycles, whereN≧2. N rising-edge latches are each connected for receiving a stream ofserial data and are each triggered at a rising edge of a different oneof the N cycles of the repeating series to take a rising-edge sample ofthe data. N falling-edge latches are each connected for receiving thedata stream and are each triggered at a falling edge of a different oneof the N cycles of the repeating series to take a falling-edge sample ofthe data. Sample processing circuitry processes the samples to recover aclock signal from the data stream.

[0021] In such clock recovery circuitry the data sampled on the fallingclock edge need not be transferred from one latch to another latchwithin half a cycle, and up to N−0.5 cycles are available. For example,when N is 4, up to 3.5 cycles are available for carrying out suchtransfer.

[0022] In such clock recovery circuitry, enabling signals needed fortriggering the rising-edge and falling-edge latches must be controlledaccurately. In one embodiment, therefore, the clock recovery circuitryhas a controller for generating N output signals, each output signalhaving an active state for an individually corresponding one of the Ncycles of the said repeating series and having an inactive state in eachnon-corresponding cycle of the series. N processing circuits areprovided, each having an input for receiving a different one of said Noutput signals, and each comprising one of the said rising-edge latchesand one of the said falling-edge latches, and also comprising an enablesignal generator having signal generating circuitry embodying theaforesaid first aspect of the present invention. The first synchronisedsignal is provided by the output signal received by the processingcircuit. One of the third and fourth synchronised signals is applied asan enabling signal to the rising-edge latch of the processing circuitand the other of the third and fourth synchronised signals is applied asan enabling signal to the falling-edge latch of the processing circuit.

[0023] In this embodiment, because the third and fourth synchronisedsignals are guaranteed to change state in particular half cycles (e.g.the third and fourth half cycles after the working edge), therising-edge and falling-edge enabling signals are guaranteed to changestate at the right times spaced apart by only half a clock cycle,irrespective of PVT variations.

[0024] A third aspect of the present invention provides verificationcircuitry, for connection to a circulating control register to verifythat a predetermined N-bit control pattern is circulating correctlythrough the register. The register has N storage elements, each forstoring one bit of the control pattern. One bit of the control patternhas a first value and each other bit has a second value. Theverification circuitry comprises a first check circuit which isconnected operatively to a first set of two or more consecutive storageelements of the register and which produces a first check signal. Thefirst check signal has a first state when any of the storage elements ofthe first set has the first value, and has a second state when all ofthe storage elements of the first set have the second value. A secondcheck circuit is connected operatively to the remaining storage elementsof the register which form a second set of two or more consecutivestorage elements. The second check circuit produces a second checksignal which has a first state when any of the storage elements of thesecond set has the first value and which has a second state when all ofthe storage elements of the second set have the second value. A samestate detection circuit is connected to the first and second checkcircuits and produces a detection signal, indicating that the controlpattern is incorrect, when the first and second check signals have thesame state.

[0025] Such verification circuitry can be implemented simply using onlysimple combinatorial logic gates such as AND or NAND gates and anexclusive OR gate. Furthermore, the loading imposed on the circulatingcontrol register by the circuitry can be desirably low, so thathigh-speed operation is not compromised.

[0026] Such a circulating control register may be used, for example, inconjunction with the above-mentioned controller in clock recoverycircuitry embodying the aforesaid second aspect of the invention or witha counter (described below) in data synchronising circuitry embodying afourth aspect of the present invention.

[0027] A fourth aspect of the present invention provides datasynchronising circuitry for receiving successively first items of dataand for outputting successively second items of data derived from thereceived first items. One of the first items is received in each cycleof a first clock signal and one of said second items is output in eachcycle of a second clock signal having a frequency N times that of thefirst clock signal, where N is an integer. A reset signal generatorcauses a reset signal to be changed from an active state to an inactivestate at a preselected point in a first-clock-signal cycle. A counter isconnected for receiving the second clock signal and the reset signal andis operable, following the change of the reset signal to the inactivestate, to count pulses of said second clock signal and to producetransfer control signals at intervals of N cycles of the second clocksignal. A data converter is connected for receiving the transfer controlsignals and the second clock signal. The data converter acceptsrespective first items in response to successive ones of the transfercontrol signals and derives the second items from the received firstitems and outputs one of the second items per second-clock-signal cycle.

[0028] The second items may be derived from the first items in anysuitable way by the data converter. The data converter may be aparallel-to-serial converter.

[0029] In such data synchronising circuitry, because the counter alwaysproduces transfer control signals at intervals of N cycles of the secondclock signal, irrespective of PVT variations, it can be guaranteed that,even if the first clock signal varies in phase relative to the secondclock signal, the first items of data will always be accepted by thedata converter at intervals fixed in relation to the second clocksignal.

[0030] A fifth aspect of the present invention provides data recoverycircuitry for sampling a received serial data stream. A clock recoverycircuit is connected for receiving a plurality of candidate clocksignals having the same frequency but spaced apart one from the next inphase. The clock recovery circuit selects, as a recovered clock signal,one of the candidate clock signals that matches the received serial datastream in phase. An offset clock circuit selects, as an offset clocksignal, a further one of the candidate clock signals different from thecandidate clock signal selected as the recovered clock signal. A datasampling circuit samples the received data stream using the offset clocksignal.

[0031] In such data recovery circuitry, the offset clock signal can bechosen freely to suit a data eye shape of the received serial datastream. The offset clock signal may have a phase lead or a phase lagwith respect to the recovered clock signal, as desired.

[0032] Because the offset clock signal is selected from amongst thecandidate clock signals it can be selected using a control signalprovided from outside the circuitry. This makes the circuitry highlyflexible.

[0033] The frequency of the candidate clock signals is preferably equalor close to the frequency of the received serial data stream.

[0034] Preferably, the selection signals used to designate one or bothof the candidate clock signals selected as the recovered clock signaland the offset clock signal is/are Gray-coded signals so thatunnecessary transitory phase jumps are avoided when the candidate clocksignal selections are changed. For the same reason it is preferable thatthe first and last candidate clock signals of the plurality differ inphase from one another by substantially the same amount as the twocandidate clock signals of each further pair of mutually-adjacentcandidate clock signals of the plurality differ in phase from oneanother.

[0035] The data recovery circuitry preferably further comprises amultiphase clock signal generator including: a delay line, connected forreceiving a reference clock signal having a frequency equal or close toa data rate of the serial data stream and having a series of individualdelay stages from which the candidate clock signals are derived; and adelay adjustment circuit for controlling a total delay imposed by thedelay stages of the series to be substantially equal to a duration ofone cycle of said reference clock signal.

[0036] In this implementation, the delay adjustment circuit ensures thatthe phases of the candidate clock signals are tightly controlledirrespective of PVT variations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037]FIG. 1 shows an example of signal generating circuitrypreviously-considered for use in clock recovery circuitry;

[0038]FIG. 2 is a timing diagram showing waveforms generated in the FIG.1 circuitry when in use;

[0039]FIG. 3 shows signal generating circuitry embodying a first aspectof the present invention;

[0040]FIGS. 4 and 5 are timing diagrams showing waveforms generated inthe FIG. 3 circuitry when in use;

[0041]FIG. 6 shows parts of clock recovery circuitry embodying a secondaspect of the present invention;

[0042]FIG. 7 is a circuit diagram showing one possible implementation ofa circulating control register in the FIG. 6 circuitry;

[0043]FIG. 8 is a circuit diagram showing one possible implementation ofan enable signal generator in the FIG. 6 circuitry;

[0044]FIG. 9 is a circuit diagram showing one possible implementation ofa rising edge latch in the FIG. 6 circuitry;

[0045]FIG. 10 is a circuit diagram showing one possible implementationof a falling edge latch in the FIG. 6 circuitry;

[0046] FIGS. 11(A) and (B) are timing diagrams showing waveformsgenerated in the FIG. 6 circuitry when in use;

[0047]FIG. 12 shows verification circuitry embodying a third aspect ofthe present invention;

[0048]FIG. 13 shows an example of previously-considered datasynchronising circuitry;

[0049]FIG. 14 is a timing diagram showing waveforms generated in theFIG. 13 circuitry when in use;

[0050]FIG. 15 shows parts of data synchronising circuitry embodying afourth aspect of the present invention;

[0051]FIG. 16 is a circuit diagram showing one possible implementationof a reset signal generator in the FIG. 14 circuitry;

[0052]FIG. 17(A) is a block diagram showing one possible implementationof a counter in the FIG. 15 circuitry;

[0053]FIG. 17(B) is a detailed circuit diagram corresponding to FIG.17(A);

[0054]FIG. 18 is a timing diagram showing waveforms generated in theFIG. 15 circuitry when in use;

[0055]FIG. 19 is a circuit diagram showing one possible implementationof a data converter in the FIG. 15 circuitry;

[0056]FIG. 20 is a timing diagram for use in explaining operation ofdata recovery circuitry; and

[0057]FIG. 21 shows parts of data recovery circuitry embodying a fifthaspect of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0058] Before describing a preferred embodiment of the invention signalgenerating circuitry previously considered for use in clock recoverycircuitry will be described with reference to FIGS. 1 and 2.

[0059] The previously-considered signal generating circuitry 10 shown inFIG. 1 comprises a first latch element 12 and a second latch element 14.Each of the latch elements 12 and 14 is, for example, apositive-edge-triggered master/slave D-type latch element.

[0060] Each of the latch elements 12 and 14 has a clock input C which isconnected to receive a clock signal CLK. Each latch element 12 and 14also has a reset input R which is connected to receive an active-lowasynchronous reset signal ARST. The reset signal ARST is asynchronouswith respect to the clock signal CLK. The first latch element 12 has adata input D which is connected to be at the high logic level H (logic1). The second latch element 14 has a data input D connected to a dataoutput Q of the first latch element 12 for receiving therefrom a firstclocked reset signal RCK1. A second clocked reset signal RCK2 isproduced at a data output Q of the second latch element 14.

[0061] The second clocked reset signal RCK2 is used, for example, as areset signal for resetting clock recovery circuitry which generatesenabling signals for bringing about sampling of data of an incomingserial data stream In such circuitry, removal of the reset signal mustbe controlled accurately in relation to the clock signal CLK.

[0062] Operation of the FIG. 1 signal generating circuitry will now bedescribed with reference to FIG. 2. In FIG. 2 it is assumed that theasynchronous reset signal ARST is initially in the low logic state L(active) and is then removed. As the ARST signal is an asynchronoussignal it can be removed at any point during a cycle of the clock signalCLK. In the example shown in FIG. 2, the ARST signal is removed at anarbitrary moment in clock cycle 0. At the first rising edge R1 followingthe removal of the ARST signal, the high state H at the D input of thefirst latch element 12 immediately before the rising edge R1 is latchedat the rising edge R1 and output from the Q output of the first latchelement 12. The first clocked reset signal RCK1 therefore changes fromthe low state L to the high state H during cycle 1. The new high state Hat the D input of the second latch element 14 just before the nextrising edge R2 is latched at that rising edge R2 by the second latchelement 14. The resulting latched H state appears at the Q output of thesecond latch element 14 later during cycle 2 and provides the secondclocked reset signal RCK2. Accordingly, in response to the removal ofthe ARST signal in cycle 0 the second clocked reset signal RCK2 changesfrom the L to the H state at a time during cycle 2 synchronised with theclock signal CLK.

[0063] Incidentally, the reason for employing two series-connected latchelements 12 and 14 in the FIG. 1 signal generating circuitry 10 is asfollows. If the first latch element 12 alone were to be provided toproduce the output signal of the circuitry (i.e. the output signal wasthe RCK1 signal instead of the RCK2 signal) it is possible that the ARSTsignal might be removed less than a predetermined minimum setup time ofthe first latch element 12 before the next rising edge (e.g. R1 in FIG.2). In this case, the RCK1 signal may enter a so-called metastable statein which it remains at between the L and H states or undergoes twoopposite changes of state following the rising clock edge. By providingthe second latch element 14 to latch the RCK1 signal just before thefollowing rising edge, there is an extremely high probability that theRCK2 signal will be a clean signal, even if the minimum setup time ofthe first latch element 12 is not met.

[0064] At frequencies approaching the limit of the circuit technologyused to construct the signal generating circuitry 10, the switching timeof each of the latch elements 12 and 14 is likely to be close to, andmay exceed, one half of a clock cycle period. This means that in FIG. 2it is not possible to guarantee in which half of cycle 2 the RCK2 signalwill change from the L to the H state across all possible PVT and othervariations. However, there are some applications in which it is vital tobe able to guarantee in which half cycle the RCK2 signal will changestate. Such applications include clock recovery circuitry.

[0065] Improved signal generating circuitry, according to an embodimentof a first aspect of the present invention, is shown in FIG. 3. In FIG.3, components of the circuitry 20 which are the same as or correspond tocomponents of the FIG. 1 signal generating circuitry 10 are denoted bythe same reference numerals, and a description thereof is omitted.

[0066] In FIG. 3, the first and second latch elements 12 and 14 arepresent and connected as described previously with reference to FIG. 1to form an input circuit 10. The second clocked reset signal RCK2 isused to provide a first synchronised signal S1. The FIG. 3 circuitryfurther comprises a third latch element 22 and a fourth latch element24. The third and fourth latch elements 22 and 24 are half (ortransparent) latch elements, each having a data input D and a dataoutput Q.

[0067] The third latch element 22 has an active-low clock input CL,whereas the fourth latched element 24 has an active-high clock input CH.Thus, the third latch element 22 has a responsive (open) state when itsclock input CL has the L state. In this responsive state the data outputQ changes in state in response to changes in state of the data input D.When the CL input has the H state the third latch element 22 is in anon-responsive (closed) state in which the data output Q does not changestate in response to changes in state at the data input D.

[0068] The fourth latch element 24, on the other hand, has theresponsive (open) state when its clock input CH has the H state, and isin the non-responsive (closed) state otherwise.

[0069] The data input D of the third latch element 22 is connected tothe data output Q of the second latch element 14 for receiving therefromthe first synchronised signal S1 (second clocked reset signal RCK2). Thedata input D of the fourth latch element 24 is connected to the dataoutput Q of the third latch element 22 for receiving therefrom a secondsynchronised signal S2. A third synchronised signal S3 is produced atthe data output Q of the fourth latch element 24. The CL and CH clockinputs of the latch elements 22 and 24 are connected for receiving theclock signal CLK.

[0070] Operation of the FIG. 3 signal generating circuitry 20 will nowbe described with reference to FIGS. 4 and 5. FIG. 4 relates to the casein which, due to processing tolerances, voltage margins and temperaturevariations (PVT variations), the circuitry (in particular the first andsecond latch elements 12 and 14 of the input circuit 10) has fastswitching times. FIG. 5 relates to the case in which, due to PVT, thesignal generating circuitry 20 has slow switching times.

[0071] In both FIGS. 4 and 5 the asynchronous reset signal ARST isassumed to be removed during a clock cycle 0 of the clock signal CLK. Asin the FIG. 1 circuitry, the RCK1 and S1 (RCK2) signals change from theL to the H state during clock cycles 1 and 2 respectively. In the fastcase (FIG. 4) it can be seen that the S1 signal changes to the H state atime t_(early) before the falling edge F2 in cycle 2. For example, whenthe frequency of the clock signal CLK is 622 MHz, t_(early) may be 0.36ns. Thus, in the fast case, the change in the S1 signal occurscomfortably in the first half of clock cycle 2.

[0072] In the slow case (FIG. 5), on the other hand, it can be seen thatthe longer switching times mean that the S1 signal only changes from theL to the H state a time t_(late) after the falling edge F2 in clockcycle 2. For example, t_(late) may be 0.03 ns when the clock frequencyis 622 MHz. Thus, in this case, the change in state of S1 occurs in thesecond half of the clock cycle 2.

[0073] In the event that S1 changes to the H state in the first half ofclock cycle 2 (i.e. in the fast case of FIG. 4), that change of statedoes not propagate through the third latch element 22 which remains inthe non-responsive state until the falling edge F2. This means that thesecond synchronised signal S2 only changes from the L to the H state ashort time t_(hl3) after the falling edge F2, that short time t_(hl3)corresponding to the switching time of the third latch element 22. Thatchange in S2, however, does not propagate immediately through the fourthlatch element 24 because that latch element is in the non-responsivestate until the rising edge R3 at the start of clock cycle 3. Thus, theS3 signal does not change from the L to the H state until a short timet_(hl4) after the rising edge R3, that short time t_(hl4) correspondingto the switching time of the fourth latch element 24. Because theswitching time t_(hl4) of the fourth latch element 24 is small comparedto the switching times t_(fl1), t_(fl2) of the first and second latchelements 12 and 14, it can be guaranteed that the S3 signal will changestate in the first half of clock cycle 3. For example, in the fast case(FIG. 4) the change in state of S3 may occur a time t_(fast) such as0.41 ns before the falling edge F3 of clock cycle 3 when the clockfrequency is 622 MHz.

[0074] In the slow case in which the S1 signal changes after the fallingedge F2 in clock cycle 2, that change propagates immediately through thethird latch element 22 during the second half of clock cycle 2 becauseat that time the third latch element 22 is in the responsive state.Thus, the S2 signal changes from the L to the H state during the secondhalf of clock cycle 2. At this time, however, the fourth latch element24 is still in the non-responsive state so that the S3 signal does notchange from its initial L state. The change in the S3 signal from the Lto the H state occurs only after the rising edge R3 when the fourthlatch element 24 enters the responsive state. The delay in the change ofstate of the S3 signal after the rising edge R3 is determined by theswitching time t_(hl4) of the fourth latch element 24. Even in theslowest case as shown in FIG. 5, that switching time t_(hl4) is lowenough to guarantee that the change in state occurs within the firsthalf of the clock cycle 3, i.e. a time t_(slow) before the falling edgeF3. For example, t_(slow) is 0.11 ns when the clock frequency is 622MHz.

[0075] Accordingly, the FIG. 3 circuitry makes it possible to guaranteethat the S3 signal at the output of the signal generating circuitry willchange state within the first half of a clock cycle irrespective ofswitching-time variations of the latch elements due to PVT and othervariations.

[0076] In the FIG. 3 circuitry, it is desired to guarantee that thechange of state of the final output signal (S3) of the signal generatingcircuitry changes state within the first half of a clock cycle. If, onthe other hand, it is desired to guarantee that the change of stateoccurs in the second half of a clock cycle, a further latch element maybe connected after the third and fourth latch elements 22 and 24 toproduce a fourth synchronised signal, that further latch element havingan active-low clock input CL. This possibility is described later withreference to FIG. 8.

[0077] Similarly, in the FIG. 3 circuitry all of the changes of stateare from L to H, but this is not essential. Any changes of state can bebrought about in any of the signals RCK1 and S1 to S3. Also, in theinput circuit 10 it is not essential for the second latch element 14 tobe provided in all cases. If the first latch element 12 comprisescircuitry for minimising or eliminating any metastable state at itsoutput RCK1 that output can be connected directly to the D input of thethird latch element 22, and the second latch element 14 can be omitted.

[0078] In place of the half latch elements any suitable clocked elementcan be used that has a switching time which is guaranteed to be fastenough to bring about a change in the synchronised signal it produceswithin the required part of a clock cycle, for example a switching timeof less than a half-cycle.

[0079] Next, parts of clock recovery circuitry 30 embodying a secondaspect of the present invention will be explained with reference toFIGS. 6 to 11.

[0080] Referring firstly to FIG. 6, the clock recovery circuitry 30comprises a circulating control register 32 having four storage elements34 ₀, 34 ₁, 34 ₂ and 34 ₃. Each storage element 34 ₀ to 34 ₃ is capableof storing a 1-bit value which is output as an output signal B0 to B3 ofthe storage element concerned.

[0081] The clock recovery circuitry 30 in FIG. 6 also has fourprocessing circuits 36 ₀ to 36 ₃, each processing circuit correspondingto one of the storage elements 34 ₀ to 34 ₃ of the circulating controlregister 32.

[0082] Each processing circuit 36 comprises an enable signal generator38, a rising edge latch 40 and a falling edge latch 42. The enablesignal generator 38 in each processing circuit 36 has an input connectedto receive the output signal B0 to B3 of the corresponding storageelement 34 ₀ to 34 ₃. The enable signal generator 38 also has a firstoutput at which a rising-edge enabling signal ENr is generated, and asecond output at which a falling-edge enabling signal ENf is generated.

[0083] The rising and falling edge latches 40 and 42 in each processingcircuit each have a data input D connected to receive a serial datastream DIN. The rising edge latch 40 has an enable input E connected toreceive the rising-edge enable signal ENr of the enable signal generator38 in its processing circuit. The falling edge latch 42 has an enableinput E connected to receive the falling-edge enabling signal ENfgenerated by the enable signal generator 38 of its processing circuit36. The rising edge latch 40 has a data output Q at which a rising-edgedata sample Dr is produced. The falling edge latch 42 has a data outputQ at which a falling-edge data sample Df is produced. The data samplesDr0 to Dr3 and Df0 to Df3 produced by the different processing circuits36 ₀ to 36 ₃ are employed by further circuits (not shown) within theclock recovery circuitry to recover a clock signal from the serial datastream DIN.

[0084]FIG. 7 shows one example of the constitution of the circulatingcontrol register 32. In the FIG. 7 example, the control register 32 ismade up of first, second, third and fourth latch elements 52, 54, 56 and58. In this embodiment, each latch element 52, 54, 56 and 58 is apositive-edge-triggered master/slave D-type latch element. Each latchelement has a data input D, a data output Q and a clock input C. Thedata input D of the first latch element 52 is connected to the dataoutput Q of the fourth latch element 58. The data input of the secondlatch element 54 is connected to the data output Q of the first latchelement 52. The data input D of the third latch element 56 is connectedto the data output Q of the second latch element 54. The data input D ofthe fourth latch element 58 is connected to the data output Q of thethird latch element 56. The respective clock inputs C of all four latchelements are connected to receive a clock signal CLK.

[0085] The first latch element 52 in FIG. 7 has an active-low resetinput R, whereas each of the second to fourth latch elements 54, 56 and58 has an active-low preset input P. The reset input R of the firstlatch element 52 and the respective preset inputs P of the second tofourth latch elements 54, 56 and 58 are connected to receive a resetsignal which, in this example, is the synchronised signal S3 produced bythe FIG. 3 signal generating circuitry embodying the aforesaid firstaspect of the present invention.

[0086] In the FIG. 7 implementation of the control register 32, eachlatch element provides one of the storage elements 34 ₀ to 34 ₃ of thecontrol register 32. Thus, the output B0 of the storage element 34 ₀ inFIG. 6 is provided at the data output Q of the first latch element 52.Similarly, the data outputs Q of the second to fourth latch elements 54,56 and 58 provide respectively the B1, B2 and B3 outputs of the controlregister 32.

[0087] In operation of the FIG. 7 control register 32, the register isinitialised by setting the S3 signal to the active (L) state. As aresult, the data output Q of the first latch element 52 is set to the Lstate, whilst each of the second to fourth latch elements 54, 56 and 58has its Q output set to the H state. Accordingly, the output signals B0to B3 are set to “0111” as shown in FIG. 6.

[0088] After the S3 signal is removed (changed to the H state) thepattern “0111” is circulated through the latch elements 52, 54, 56 and58 in response to each rising edge of the CLK signal. Thus, the outputsignals B0 to B3 become “1011”, “1101”, “1110” and then “0111” again ina repetitive manner. In particular, each output signal B0 to B3 has theL state for one clock cycle in every four, and over a series of fourconsecutive cycles the four different output signals take the L state inturn.

[0089] Next, an example of the implementation of the enable signalgenerator 38 in each processing circuit 36 ₀ to 36 ₃ will be explainedwith reference to FIG. 8. In the FIG. 8 example it will be assumed thatthe enable signal generator 38 is the enable signal generator of thefirst processing circuit 36 ₀ which receives the output signal B0 of thecirculating control register 32. The enable signal generators in theremaining processing circuits 36 ₁ to 36 ₃ are constituted in the sameway as the enable signal generator 38 of FIG. 8 but receive the outputsignals B1 to B3 instead.

[0090] The FIG. 8 enable signal generator 38 is based on the FIG. 3signal generating circuitry and comprises respective first, second andthird latch elements 62, 64 and 66. In this case, the input circuit 10in FIG. 3 is not used. The first latch element 62 in FIG. 8 correspondsto the third latch element 22 in FIG. 3; the second latch element 64 inFIG. 8 corresponds to the fourth latch element 24 in FIG. 3; the thirdlatch element 66 in FIG. 8 is an additional latch element not present inFIG. 3. This additional latch element is also a half (or transparent)latch element.

[0091] Each latch element 62, 64 and 66 has a data input D and a dataoutput Q. The first and third latch elements 62 and 66 each have anactive-low clock input CL, and the second latch element 64 has anactive-high clock input CH. The data input D of the first latch element62 is connected for receiving the output signal B0 of the circulatingcontrol register. The data input D of the second latch element 64 isconnected to the data output Q of the first latch element 62 forreceiving therefrom a clocked output signal BCK0. The data input D ofthe third latch element 66 is connected to the data output Q of thesecond latch element 64. The above-mentioned rising-edge enabling signalENr0 is produced at the data output Q of the second latch element 64,and the above-mentioned falling-edge enabling signal ENf0 is produced atthe data output Q of the third latch element 66. The clock input CL orCH of each latch element 62, 64 and 66 is connected for receiving theclock signal CLK. It will be appreciated that the B0 signal in FIG. 8corresponds to the first synchronised signal S1 in FIG. 3; the BCK0signal corresponds to the second synchronised signal S2 in FIG. 3; andthe ENr0 signal corresponds to the third synchronised signal S3 in FIG.3.

[0092] Before describing the operation of the FIG. 8 enable signalgenerator an example of the implementation of the rising edge latch 40and the falling edge latch 42 in the processing circuit 36 ₀ will begiven with reference to FIGS. 9 and 10, in order that the operation ofthe processing circuit 36 ₀ as a whole can be explained.

[0093] In FIG. 9 the rising edge latch 40 is a positive-edge-triggeredmaster-slave D-type flip-flop. The flip-flop 40 has a data input D whichreceives the serial data stream DIN; an enable input E which receivesthe rising-edge enable signal ENr0; a clock input C which receives theclock signal CLK; and a data output Q at which the above-mentionedrising-edge data sample Dr0 is generated. The enable input E is used toswitch the flip-flop 40 between an enabled state and a disabled state.In the enabled state (enable input E in the L state) the state of the Dinput immediately before each rising edge of the CLK signal istransmitted to the data output Q. In the disabled state (enable input Ein the H state) the flip-flop 40 is not responsive to the data input D.

[0094] The falling-edge latch 42 of FIG. 10 is a negative-edge-triggeredD-type flip-flop which, apart from being triggered on the falling edgesof the clock signal CLK, otherwise operates in the same basic way as theflip-flop 40 of FIG. 9.

[0095] Operation of the FIGS. 6 to 10 circuitry will now be describedwith reference to FIGS. 11(A) and 11(B). The clock cycles of the clocksignal CLK form a repeating series of four consecutive cycles A0-A3,B0-B3, C0-C3 etc., each new cycle starting at a rising edge of the clocksignal. In FIGS. 11(A) and (B), only the cycles A1-A3, B0-B3 and C0-C1are illustrated.

[0096] When the CLK signal rises at the time A the cycle A2 begins. Atthis time, the content of the control register 32 is 1110 (i.e. B0=1,B1=1, B2=1 and B3=0). The contents of the control register 32 justbefore the rising edge are shifted one storage element to the right inFIG. 6, with the content of the right-hand-most storage element 34 ₃being transferred into the left-hand-most storage element 34 ₀. Thus, inthis case, changes occur in the B0 and B3 signals at around a time Bduring clock cycle A2. Depending on the switching time of the latchelements 52, 54, 56 and 58 in FIG. 7, the time B could be in the firsthalf of clock cycle 2 (as shown) or in the second half of clock cycleA2, as described previously with reference to FIG. 5. This variation isnot important, for reasons that will be explained later.

[0097] Each signal B0 to B3 is passed to its corresponding one of theprocessing circuits 36 ₀ to 36 ₃.

[0098] The latch element 62 in each enable signal generator 38 is in anon-responsive state until the second half of clock cycle A2 begins(time C). This means that it is guaranteed that any changes in the B0 toB3 signals do not appear in the corresponding clocked signals BCK0 toBCK3 until a time D during the second half of clock cycle A2. Even ifthe changes in the signals B0 to B3 occur shortly after time C (as ispossible if the latch elements 52, 54, 56 and 58 have long switchingtimes due to PVT variations), it is still guaranteed that thecorresponding changes in the clocked signals BCK0 to BCK3 will occurwithin the second half of clock cycle A2.

[0099] Any change in the BCK0 to BCK3 signals is prevented frompropagating further until the first half of cycle A3 begins at time E.At that time, the latch element 64 in FIG. 8 changes from thenon-responsive state to the responsive state so that the rising-edgeenabling signals ENr0 to ENr3 undergo changes of state at a time Fduring the first half of clock cycle A3, those changes reflecting thechanges in B0 to B3 which occurred at time B.

[0100] It is thus guaranteed that the rising-edge enabling signal ENr0becomes active during the first half of clock cycle A3. That rising-edgeenabling signal ENr0 is used to take a rising-edge sample Dr0 of theserial data stream DIN at time J, i.e. at the beginning of clock cycleB0. The rising edge latch 40 in the processing circuit 36 ₀ thereforehas a sufficient set-up time from the time F at which the enable signalENr0 becomes active to the sampling time J. This set-up time isguaranteed to be at least half a clock cycle. Thus, at time J the stateof the DIN serial data stream (L state) is sampled and is latched in therising edge latch 40 of the first processing circuit 36 ₀. The sampleddata Dr0 is available at the output of that latch 40 shortly after timeJ.

[0101] At time I during cycle A3, the falling-edge enabling signal ENf0changes to the active L state. Again, this change is guaranteed to occurin the second half of cycle 2 because the latch element 66 in FIG. 8 ismaintained in the non-responsive state until the second half of eachcycle. This means that the change in the rising-edge enabling signalENr0 at time F does not propagate through the latch element 66 until thetime I. The change of state of the falling-edge enabling signal ENf0causes a falling-edge sample Df0 to be taken in cycle B0 at time K. Thissample reflects the state of the DIN data stream just before the time K,i.e. the H state. The resulting data sample Df0 becomes available at theoutput of the falling edge latch 42 in the processing circuit 36 ₀ attime L just before the end of cycle B0. Again, the enable set-up timefor the falling edge latch 42 (from time I to time K) is guaranteed tobe at least half a clock cycle.

[0102] In the next cycle B1 a new rising-edge data sample Dr1 is takenat time M, and a new falling-edge data sample Df1 is taken at time N. Incycle B2 a new rising-edge data sample Dr2 is taken at time O and a newfalling-edge data sample Df2 is taken at time P. In clock cycle B3 a newrising-edge data sample Dr3 is taken at time Q and a new falling-edgedata sample is taken at time R.

[0103] It will be appreciated that the enable signal generator 38 alsoserves to ensure that, irrespective of PVT variation, each enablingsignal ENr or ENf is changed to the inactive H state within half a cycleof the relevant rising or falling edge to which it relates. For example,the rising-edge enabling signal ENr0 is changed to the inactive statewithin half a cycle of the falling edge of cycle B0 (time J).

[0104] It will be appreciated that in FIGS. 11(A) and (B) the rising andfalling edge latches 40 and 42 of each processing circuit 36 takesamples within half a clock cycle of one another. However, each latch isonly updated once in every four clock cycles. For example, the latch 40in the first processing circuit 36 ₀ is next updated in cycle C0 of thenext series of four cycles C0-C3. This strategy allows about 3.5 clockcycles (rather than 0.5 clock cycles as in previously-considered clockrecovery circuitry) before the data samples must be transferred again toother latches or evaluated directly, which makes the further circuitrywhich processes the data samples much simpler to design.

[0105] In the embodiment of FIGS. 6 to 11, the circulation controlregister 32 has four storage elements and there are four processingcircuits. However, other embodiments of the second aspect of the presentinvention can have different numbers of storage elements and processingcircuits. For example, the number of storage elements and processingcircuits could be any integer greater than or equal to 2. In general,when the number of storage elements and processing circuits is N, N−0.5clock cycles are available before the data samples must be transferredagain to other latches or evaluated directly.

[0106] As shown in FIG. 7 it is preferable that the reset signal appliedto the circulating control register 30 in the initialisation operationbe provided by signal generating circuitry as shown in FIG. 3. Inparticular, as the S3 signal produced by the FIG. 3 circuitry isguaranteed to change state in the first half of a clock cycle,irrespective of PVT variations, the set-up time before normal operationstarts (with 0111 in the circulating control register 32) is guaranteedto be at least half a clock cycle.

[0107] In embodiments of the second aspect of the invention it isimportant that the circulating control pattern (0111) does not becomecorrupted, since, if it does, the data samples will be taken at thewrong times and as a result the ability to recover a clock signal fromthe incoming serial data stream DIN will be lost. In view of thisproblem, it is desirable to provide verification circuitry capable ofverifying that the correct control pattern is circulating through thecontrol register 32.

[0108]FIG. 12 shows one example of such verification circuitry 80. Thecircuitry 80 comprises respective first and second NAND gates 82 and 84,an equivalence (exclusive-OR) gate 86 and a flip-flop 88. The first NANDgate 82 is connected to receive the output signals B0 and B1 belongingto a first half of the control register 32. The second NAND gate 84 isconnected to receive the outputs signals B2 and B3 of the second half ofthe control register 32. An output of the first NAND gate 82 isconnected to a first input of the equivalence gate 86 for applyingthereto a first-half check signal H1. An output of the second NAND gate84 is connected to a second input of the equivalence gate 86 forapplying thereto a second-half check signal H2. An output of theequivalence gate 86 is connected to a data input D of the flip-flop 88for applying thereto a detection signal SAME. The flip-flop 88 also hasa clock input C which is connected to receive the clock signal CLK, anda data output Q at which an error signal ERR is produced.

[0109] The verification circuitry 80 of FIG. 12 operates as follows. Itis assumed that the control register 32 will continue to shift, even ifthe control sequence becomes corrupted. The control register 32 isdivided into two halves which are checked separately. The resultingcheck signals for the two halves should always be different. If they arethe same then corruption of the control sequence must have occurred.

[0110] The output signals B0 and B1 of the first half of the controlregister are NANDed together to produce the first-half check signal H1.Similarly, the second-half output signals B2 and B3 are NANDed togetherto produce the second-half check signal H2. If the control sequence iscorrect, only one of the check signals H1 and H2 can have the H state(corresponding to at least one 0 in the register half concerned). Theother check signal must have the L state (corresponding to all outputsignals in that register half being 1). The equivalence gate 86 sets thedetection signal SAME to the L state when the check signals H1 and H2are in the same state, and sets the detection signal SAME to the H statewhen the check signals H1 and H2 have different states. The state of theSAME signal just before each rising edge of the CLK signal is sampled bythe flip-flop 88, and this state is used to provide the ERR signal. Inthis way, the SAME signal is only sampled once the check signals H1 andH2 have stabilised following a circulation operation of the controlregister 32. The ERR signal is an active-low signal in this embodiment(because the SAME signal has the L state when the two check signals H1and H2 have the same state, which represents corruption of the controlsequence).

[0111] It will be appreciated that, because of its simplicity, theverification circuitry 80 of FIG. 12 does not positively verify thecorrectness of the control pattern in each cycle of the repeating seriesof cycles (e.g. a series of four cycles such as cycles B0 to B3 in theFIG. 6 embodiment). Thus, not all errors will be detected immediately.Nonetheless, every type of error will eventually be detected. Inparticular, if the control pattern becomes corrupted such that alloutput signals become 1, this will be detected immediately. If thecontrol pattern becomes corrupted such that more than one output signalbecomes zero this will be detected when a zero exists in each half ofthe control register. Thus, any incorrect number (0, 2, 3, 4 in the FIG.6 embodiment) of circulating zeros will be detected within a smallnumber of cycles (at most equal to the length of the pattern) withoutthe need to search explicitly for a particular correct pattern in eachcycle.

[0112] Although in the FIG. 12 embodiment the verification circuitry isadapted to check the correctness of a four-bit control register, it willbe understood that other embodiments of the verification circuitry canbe produced to work with control registers having a number of bitsgreater than 4. The two “halves” need not have equal numbers of bits.For example, with a control sequence of length 5 bits, the two halvescould have 2 bits and 3 bits respectively (i.e. a 2-input NAND gate anda 3-input NAND gate). The two halves also do not have to begin and endwith the first and last bits of the control register. As the controlpattern circulates, the first and last bits could be in the same half.For example, with 4 bits one half could be the end bits 3 and 0 and theother half could be the intermediate bits 1 and 2.

[0113] The advantages of the verification circuitry are particularlystrong for control registers having large numbers of bits, for example 8bits or more. In this case, verification circuitry capable of positivelyidentifying explicit correct states in all cycles would be complicatedand, because of the large number of gates involved, would tend to imposean undesirably heavy load on the output signals of the control registerwhich may be incompatible with satisfactory high-speed operation.

[0114] In place of the two NAND gates, two AND gates could be used.Alternatively, one NAND gate and one AND gate could be used.

[0115] The verification circuitry of FIG. 12 can be adapted to verifythe correctness of a circulating control sequence having a single 1 withall other bits being 0 (as opposed to a single 0 with all other bitsbeing 1). In this case, the first and second NAND gates 82 and 84 arereplaced by NOR or OR gates.

[0116] Next, embodiments of a fourth aspect of the present inventionwill be described. The fourth aspect of the present invention canprovide a solution to a problem arising in previously-consideredparallel-to-serial data conversion circuitry. FIG. 13 shows an exampleof a data synchronising circuit 90 in a previously-consideredparallel-to-serial data converter. The synchronising circuit 90 is aso-called standard double buffer circuit having respective first andsecond master/slave latch elements 92 and 94. Each latch element 92 and94 has a clock input C which is connected for receiving a serial clocksignal SERCLK. A parallel clock signal PARCLK is applied to a data inputD of the first latch element 92. A data output Q of the first latchelement 92 is connected to a data input D of the second latch element 94for applying thereto a buffered parallel clock signal BPCLK. A dataoutput Q of the second latch element 94 is connected to a control inputof the shift register 96 for applying thereto a transfer control signalTFER. The serial clock signal SERCLK is also applied to a clock input ofthe shift register 96. The shift register 96 has a parallel data inputfor receiving an item PARDATA of parallel data, and a serial data outputfor producing a serial output data stream DOUT.

[0117] In operation, the parallel data is permitted to change at risingedges only of the parallel clock signal PARCLK. Each item of paralleldata is made up of 8 bits in this example so that the serial clockfrequency is 8 times the parallel clock frequency. Thus, in each cycleof the parallel clock signal PARCLK there are 8 cycles of the serialclock signal SERCLK which are numbered as cycles 0 to 7 in FIG. 14.

[0118] The parallel clock signal PARCLK changes to the L state duringcycle 4 of the serial clock signal SERCLK. Thus, at the beginning ofcycle 5 this change is detected and the BPCLK signal changes from H toL. This means that at the beginning of cycle 6 the transfer controlsignal TFER changes from H to L. The control input of the shift register96 detects the TFER level change so that in cycle 7 a new item PARDATAof parallel data is loaded into the shift register 96. In cycle 7 and ineach subsequent cycle of the serial clock signal SERCLK (i.e. cycles 0to 6 of the next parallel clock cycle) 1 bit of the item loaded at thebeginning of cycle 7 is transferred out of the shift register as serialdata DOUT. Then, at the beginning of cycle 7 of the next parallel clockcycle the TFER signal has its next falling edge, so that the next itemPARDATA of parallel data is loaded into the shift register.

[0119] In practice, at frequencies approaching the limit of thetechnology, it is very difficult to control the relative phase of theserial clock signal SERCLK with respect of that of the parallel clocksignal PARCLK. Accordingly, although the serial clock cycle at which theparallel clock is first detected to have become in the L state should beclock cycle 5, it is possible that the parallel clock signal might bedetected as being in the L state by the beginning of clock cycle 4. Thiscould occur if the falling edge of the parallel clock signal PARCLKoccurs just before the rising edge of the serial clock signal SERCLK incycle 4. In this case the BPCLK and TFER signals change one cycleearlier, as shown by the dotted lines in FIG. 14. In the worst case, thedetection could occur in either cycle 4 or cycle 5 on a random basis.This would result in the transfer control signal TFER being generated atvarying intervals of 7, 8 or 9 cycles of the serial clock signal SERCLK,with either loss or duplication of bits in the serial data stream DOUT.

[0120] To avoid this problem, data synchronising circuitry embodying afourth aspect of the present invention can be used.

[0121]FIG. 15 shows an embodiment of such data synchronising circuitry.The circuitry 100 comprises a reset signal generator 102, a counter 104,and a data converter 106. The reset signal generator 102 receives both aparallel clock signal PARCLK and a serial clock signal SERCLK. In thisembodiment it will be assumed that each item of parallel data to beserialised in a single clock cycle of the parallel clock signal PARCLKis made up of 8 bits, so that the clock frequency of the serial clockSERCLK is 8 times that of the parallel clock signal PARCLK.

[0122] The reset signal generator 102 receives a reset signal ARST whichis removed (changed to an inactive state) asynchronously with respect toboth the parallel and serial clock signals. The reset signal generator102 applies a synchronised reset signal SRST to the counter 104. Thesynchronised reset signal SRST is synchronised with respect to theserial clock signal SERCLK. The counter 104 is maintained in a resetcondition when the SRST signal is in an active state and is released tostart counting pulses of the serial clock signal SERCLK when the SRSTsignal is changed by the reset signal generator 102 to the inactivestate.

[0123] The counter 104 counts the number of pulses of the serial clocksignal SERCLK received after the synchronised reset signal SRST isremoved. After the count value reaches 7 the count value is reset tozero again. The counter 104 applies a transfer control signal TFER tothe data converter 106. When the count value has a predetermined value,for example the value 3, the transfer control signal TFER is set to theactive state. For all other count values the transfer control signalTFER has the inactive state.

[0124] The data converter 106 has a parallel data input for receiving an8-bit item of parallel data. Each time the transfer control signal TFERis set to the active state by the counter 104 a new item PARDATA ofparallel data is transferred into and stored in the data converter 106.The data converter 106 in this embodiment also has a serial data outputat which a stream of serial data DOUT is produced. The data converter106 receives the serial clock signal SERCLK and, when the transfercontrol signal TFER is in the inactive state, the bits of the storeditem of parallel data in the data converter 106 are shifted out oneafter the next from the serial data output, one bit being output in eachclock cycle of the serial clock signal SERCLK.

[0125] In the FIG. 15 data synchronising circuitry, because the counter104 counts actual pulses of the serial clock signal, the transfercontrol signal TFER is guaranteed to be generated at intervals of eightcycles of the serial clock signal SERCLK irrespective of PVT variationsin the circuitry. Thus, duplication or loss of data bits does not occurin the serialisation process.

[0126]FIG. 16 shows an example of the implementation of the reset signalgenerator 102 in the FIG. 15 embodiment. In this implementation thereset signal generator 102 comprises first, second, third and fourthlatch elements 110, 112, 114 and 116. Each of the latch elements is ofthe master/slave type and has a data input D, a clock input C, a resetinput R and a data output Q. The first and second latch elements 110 and112 form a first synchronising circuit 118 ₁ whose pair of latchelements is clocked by the parallel clock signal PARCLK. The third andfourth latch elements 114 and 116 form a second synchronising circuit118 ₂ whose pair of latch elements is clocked by the serial clock signalSERCLK. All four latch elements receive at their respective reset inputsR the asynchronous reset signal ARST which, in this embodiment, is anactive-low signal.

[0127] The data input D of the first latch element 110 is setpermanently to the H state. The data output Q of the first latch element110 is connected to the data input D of the second latch element 112 forapplying thereto a rising signal PR synchronised with the parallel clocksignal PARCLK. The data output Q of the second latch element 112 isconnected to the data input D of the third latch element for applyingthereto a detection signal DET synchronised with the parallel clocksignal PARCLK. The data output Q of the third latch element 114 isconnected to the data input D of the fourth latch element 116 forapplying thereto a rising signal SR synchronised with the serial clocksignal SERCLK. The synchronised reset signal SRST is produced at thedata output Q of the fourth latch element 116.

[0128] FIGS. 17(A) and (B) show an example of the implementation of thecounter 104 in the FIG. 15 embodiment. As shown in FIG. 17(A) thecounter 104 may be implemented as a circulating control register 120similar to the circulating control register 32 in FIG. 6. In this case,the circulating control register 120 needs to have eight bits (one foreach bit of the parallel data to be serialised per parallel clock signalcycle). Thus, as shown in FIG. 17(A) the circulating control register120 has eight storage elements 122 ₀ to 122 ₇. Only an output signal B3of the storage element 122 ₃ is used in this embodiment. This outputsignal B3 may be used to provide the transfer control signal TFERdirectly. Alternatively, the transfer control signal TFER may beprovided by passing an output signal of the circulating control register120 through elements 22 and 24 in FIG. 3 (or elements 62, 64 and 66 inFIG. 8) In this case, the output signal may be the signal B2, instead ofthe signal B3. This measure can assist in meeting the setup timerequirements of the logic used to parallel load the shift register. Inthis case, the intermediate circuitry is not needed to ensure thatswitching of TFER occurs in a particular half cycle (although this isguaranteed); the purpose is simply to guarantee that the setup timerequirements will be met irrespective of PVT variations.

[0129] As shown in FIG. 17(B) the constitution of the control register120 is essentially the same as that of the circulating control registerdescribed previously with reference to FIG. 7, there being amaster/slave latch element 124 ₀ to 124 ₇ for each storage element 122 ₀to 122 ₇. The latch element 124 ₀ has a reset input R which is connectedto receive the synchronised reset signal SRST. Each of the remaininglatch elements 124 ₁ to 124 ₇ has a preset input P which is connected toreceive the synchronised reset signal SRST. Thus, when the synchronisedreset signal SRST is in the active L state the output signals B0 to B7of the latch elements 124 ₀ to 124 ₇ are initialised to 01111111 asshown in FIG. 17(A). After the synchronised reset signal SRST is removed(changed to the H state) the control pattern is shifted in circularmanner one position to the right in FIG. 17(A) in response to eachrising edge of the serial clock signal SERCLK.

[0130] Operation of the reset signal generator 102 of FIG. 16 and thecounter 104 (implemented as the circulating control register 120 ofFIGS. 17(A) and (B)) will now be described with reference to FIG. 18. InFIG. 18 the parallel data PARDATA is assumed to change at rising edgesof the parallel clock signal PARCLK. The eight cycles of the serialclock signal SERCLK in a given cycle of the parallel clock signal PARCLKare numbered from 0 to 7 in FIG. 18.

[0131] In FIG. 18 a new cycle P0 of the parallel clock signal PARCLKbegins at a time A. At a time B during that cycle P0 the reset signalARST is removed, i.e. the ARST signal is changed to the inactive H statefrom the active L state. The inactive state of the ARST signal justbefore the start of the next parallel clock cycle P1 at time C isdetected and latched by the first latch element 110 at time C. At timeD, shortly after the start of that next parallel clock cycle P1, theparallel-clock-synchronised rising signal PR changes from the L to the Hstate.

[0132] The same change occurs in the detection signal DET at a time Fshortly after the start (at time E) of the next parallel clock cycle P2.The response by the third latch element 114 depends on the temporalrelationship between the serial clock SERCLK and theparallel-clock-synchronised detection signal DET. The normal temporalrelationship is as shown in FIG. 18. In this normal case, in theparallel clock cycle P2 commencing at time E the rising edge SRE of thefirst cycle (cycle 0) of the serial clock signal SERCLK occurs beforethe rising edge PRE of the parallel-clock-synchronised detection signalDET. In this case, the change in state from L to H of DET is notregistered by the third latch element 114 until the rising edge of theserial clock signal SERCLK at time G. Thus, theserial-clock-synchronised rising signal SR changes from the L to the Hstate in serial clock cycle 1 just after time G, and the synchronisedreset signal SRST undergoes the same change at a time H, just after thebeginning of the serial clock cycle 2. This means that the first risingedge of the serial clock signal SERCLK at which the counter 104 startsto count is the rising edge at time I, i.e. the start of serial clockcycle 3. Accordingly, the output signal B3 (TFER) of the counter 104becomes L for one cycle in serial clock cycle 5. Thereafter, even if thephase relationship between the parallel clock signal PARCLK and theserial clock signal SERCLK changes (e.g. due to voltage or temperaturevariation) it is guaranteed that the output signal B3 will become L forone serial clock cycle at intervals of exactly eight serial clockcycles.

[0133] Because of PVT variation, it is possible that the rising edge SREcould occur after the rising edge PRE. In this case, the change from Lto H state in each of the signals SR and SRST will occur one serialclock cycle earlier than in FIG. 18, i.e. the change in SR will takeplace shortly after the beginning of serial clock cycle 0 and the changein SRST will occur shortly after the start of serial clock cycle 1. Thisin turn will mean that the counter 104 begins to count one serial clockcycle earlier, so that the output signal B3 will become low in serialclock cycle 4 instead of serial clock cycle 5. However, this differenceis of no consequence for correct operation of the circuitry. Theparallel data PARDATA will be equally stable in clock cycle 4 as it isin clock cycle 5. Also, the interval between successive active cycles ofthe output signal B3 (TFER) of the counter 104 is still guaranteed to beexactly eight serial clock cycles, even if the phase relationshipbetween the parallel and serial clock signals changes or fluctuates fromone parallel clock cycle to the next due to voltage and temperaturevariation.

[0134] Next, an example of the possible constitution of the dataconverter 106 will be described with reference to FIG. 19.

[0135] In the FIG. 19 example, the data converter 106 comprises eightmultiplexer elements 130 ₀ to 130 ₇ and eight latch elements 132 ₀ to132 ₇. Each multiplexer element 130 has first and second data inputs I0and I1, a selection input S and a data output Z. The first data input I0of each multiplexer element 130 ₀ to 130 ₇ is connected for receivingone bit PARDATA0 to PARDATA7 of the parallel data PARDATA to beserialised. The second data input I1 of the multiplexer element 130 ₀ isset permanently (but arbitrarily) to the H state (logic 1). The seconddata input I1 of each of the remaining multiplexer elements 130 ₁ to 130₇ is connected for receiving a shift data signal SD0 to SD6 produced byan immediately-preceding one of the latch elements 132 ₀ to 132 ₆. Thetransfer signal TFER is applied to each of the selection inputs S.

[0136] Each latch element has a data input D, a data output Q and aclock input C. The data input D of each latch element 132 ₀ to 132 ₇ isconnected to the data output Z of its corresponding one of themultiplexer elements 130 ₀ to 130 ₇ for receiving a multiplexed outputsignal M0 to M7 of that multiplexer element. The above-mentioned shiftdata signals SD0 to SD6 are produced respectively at the data outputs Qof the latch elements 132 ₀ to 132 ₆. The serial data stream DOUT isproduced at the data output Q of the latch element 132 ₇. The clockinput C of each latch element 132 ₀ to 132 ₇ is connected for receivingthe serial clock signal SERCLK. In this embodiment, each latch element132 ₀ to 132 ₇ is a positive-edge-triggered master/slave latch element.

[0137] In operation of the FIG. 19 data converter, each multiplexerelement 130 ₀ to 130 ₇ selects its first data input I0 when itsselection input S has the L state, and otherwise selects the second datainput I1. The data at the selected input I0 or I1 is output at the dataoutput Z. Accordingly, when the transfer control signal TFER has the Lstate the multiplexed output signals M0 to M7 become equal to theparallel data bits PARDATA0 to PARDATA7 respectively. These multiplexedoutput signals M0 to M7 are registered in the latch elements 132 ₀ to132 ₇ respectively at the rising edge of the serial clock signal SERCLKat the start of serial clock cycle 6 in FIG. 18 (time J). Thus, in cycle6 SD0=PARDATA0, SD1=PARDATA1, . . . SD6=PARDATA6. As DOUT=PARDATA7, themost significant bit PARDATA7 of the parallel data is output into theserial data stream DOUT in cycle 6.

[0138] Shortly after time J in FIG. 18, the TFER control signal revertsto the H state so that M0 equals 1, M1=SD0, M2=SD1, . . . and M7=SD6.This set of signals MO to M7 is registered in the latch elements 132 ₀to 132 ₇ at the next rising edge of the serial clock signal SERCLK, i.e.at the start of clock cycle 7. The parallel data bit PARDATA6 is outputinto the serial data stream DOUT in cycle 7.

[0139] In successive serial clock cycles each of the further bitsPARDATA5 to PARDATA0 are output sequentially into the serial data streamDOUT. Then, in the next serial clock cycle, which is guaranteed to beexactly eight clock cycles after the clock cycle at time J in FIG. 18,the TFER control signal takes the L state again for one cycle, and a newitem of parallel data is loaded into the latch elements 132 ₀ to 132 ₇.

[0140] In the embodiment of FIGS. 15 to 19 the data converter is aparallel-to-serial data converter. However, this is not an essentialfeature of the fourth aspect of the invention. The data converter can beadapted to convert generally first items of data into second items ofdata, the first items being received successively in synchronism with afirst clock signal and the second items being output successively insynchronism with a second clock signal of higher frequency than thefirst clock signal. Both the first and second items may be paralleldata. The conversion operation performed by the data converter is notlimited in any way. Any number of first items may be used to produce anynumber of second items. The conversion operation may involve inversionor combinatorial logic operations on the bits of the received firstitems to produce the second items.

[0141] The design of the converter 104 is not limited to a circulatingcontrol register as shown in FIGS. 17(A) and (B). Any converter capableof counting clock pulses can be used.

[0142] When a circulating control register is used to provide thecounter 104, verification circuitry embodying the third aspect of theinvention is preferably used to verify that the control pattern iscirculating correctly through the register.

[0143] Next, an embodiment of data recovery circuitry embodying a fifthaspect of the present invention will be described with reference toFIGS. 20 and 21. In FIG. 20 a serial data stream, received at datarecovery circuitry, has a data eye 150 of a shape dependent, forexample, on a characteristic of a transmission path carrying the serialdata stream. In the data recovery circuitry, a clock signal 152 isrecovered from the serial data stream using a phase lock loop (PLL)circuit, for example. This recovered clock signal matches the serialdata stream in phase. In previously-considered data recovery circuitry,the recovered clock signal 152 is then used to latch the serial datastream.

[0144] However, depending on the shape of the data eye of the serialdata stream, it may be better to use a clock signal which is offset fromthe recovered clock signal 152 to perform the latching of the serialdata stream. For example, in the case of the data eye 150 in FIG. 20, anoffset clock signal 154 which is delayed by an amount ΔT with respect tothe recovered clock signal 152 would be better to use to latch theserial data stream. One possible way of producing the offset clocksignal 154 would be to delay the recovered clock signal 152 using adelay element. However, in practice, producing the offset clock signalthis way has disadvantages. In particular, the delay ΔT is hard tocontrol across process, voltage and temperature (PVT) variations. Also,the delay cannot easily be controlled from outside the data recoverycircuitry. Furthermore the offset clock signal 154 can only be delayedrelative to the recovered clock signal 152 and cannot be advancedrelative to it when a delay element is used.

[0145]FIG. 21 shows an embodiment of data recovery circuitry embodying afifth aspect of the present invention. In the FIG. 21 embodiment, thedata recovery circuitry 160 comprises a multiphase clock signalgenerator 170, a digital phase lock loop (DPLL) circuit 180, a firstmultiplexer element 190, a second multiplexer element 200, a data latchelement 210, and an adder 220.

[0146] The multiphase clock signal generator 170 comprises a delay line172, a phase detector 174, a charge pump voltage regulator 176 and aphase interpolator 178.

[0147] The delay line 172 in this embodiment has a series of eight delaystages, together with an input buffering stage, preceding the firstdelay stage of the series, and an output buffering stage following thelast (eighth) stage of the series. The delay line 172 has a signal inputIN at which a reference clock signal REFCLK, equal or close to the datarate of the incoming serial data stream, is received into the inputbuffering stage. The delay stages impose equal delays. In thisembodiment, the clock frequency of the reference clock signal is 622.08MHz (corresponding to a clock period of 1.6075 ns). The delay line 172also has a control input DLYCTRL at which an analog control voltageV_(reg), used to fractionally adjust a delay time imposed by each delayelement, is received. First and second phase comparison signals P1 andP2 are output by the delay line 172 to a phase detector 174. The firstphase comparison signal P1 is the buffered signal at the input of thefirst delay stage (i.e. after the input buffering stage of the delayline 172). The second phase comparison signal P2 is produced at anoutput of the last (eighth) delay stage.

[0148] In the phase detector 174 the respective phases of the first andsecond phase comparison signals P1 and P2 are compared. The delay of thesecond phase comparison signal P2 relative to the first phase comparisonsignal P1 is intended to be maintained at exactly one clock cycle of thereference clock signal REFCLK (i.e. a nominal total delay imposed by thedelay line is 1.6075 ns). Thus, the second phase comparison signal P2should be inphase with the first phase comparison signal P1 (but delayedby one full clock cycle relative thereto).

[0149] The phase detector 174 produces one of two control signals FASTand SLOW according to the result of the phase comparison between thesignals P1 and P2. When the phase of the signal P2 is ahead of that ofthe signal P1 the FAST control signal is produced by the phase detector174. When, on the other hand, the phase of the signal P2 is behind thatof the signal P1 the SLOW control signal is produced by the phasedetector 174. The phase detector 174 preferably comprises windowdetection circuitry which rejects locking on multiples or harmonics ofthe reference clock signal frequency.

[0150] The FAST and SLOW control signals are applied to the charge pumpvoltage regulator 176 which produces at its output the control voltageV_(reg). The regulator 176 contains a capacitor. The amount of chargeheld in the capacitor is increased when the SLOW control signal isproduced. Similarly, the amount of charge held in the capacitor isdecreased when the FAST control signal is produced. The control voltageV_(reg) is derived from the voltage across the capacitor. The delayimposed by each delay stage in the delay line 172 is dependent on thecontrol voltage V_(reg). When the control voltage V_(reg) decreases,indicating that the phase of the second phase comparison signal P2 isahead of that of the first comparison phase signal P1, the delay imposedby each delay stage increases. When, on the other hand, the controlvoltage V_(reg) increases, indicating that the phase of the second phasecomparison signal P2 is behind that of the first phase comparison signalP1, the delay imposed by each delay stage is decreased. Accordingly, thephase detector 174 and charge pump voltage regulator 176 form a feedbackloop around the delay line 172, which operates to maintain or lock thetotal delay imposed by the eight delay stages of the delay line 172 atexactly one clock cycle of the reference clock signal REFCLK,irrespective of PVT variation.

[0151] The phase interpolator 178 receives nine basic phase signalsproduced by the delay line 172. The first basic phase signal is thesignal produced at the output of the input stage of the delay line 172,i.e. the first phase comparison signal P1. The remaining eight basicphase signals are the delayed signals produced respectively at theoutputs of the eight delay stages of the delay line 172. Thus, the ninthbasic phase signal is the second phase comparison signal P2.

[0152] For each pair of adjacent basic phase signals the phaseinterpolator 178 produces a further three interpolated phase signalswith evenly-spaced phases between the respective phases of the two basicphase signals of its pair. Thus, the phase interpolator 178 generates 24interpolated phase signals, in addition to the nine basic phase signalsgenerated by the delay line 172. The difference in phase between thebasic and interpolated phase signals and between adjacent interpolatedphase signals is {fraction (1/32)} of the reference clock signalfrequency, i.e. 50.23 ps in this embodiment.

[0153] One of the two “end” basic phase signals is discarded, as both ofthem are in-phase with the reference clock signal REFCLK. The remainingone of the “end” basic phase signals, for example the basic phase signalproduced at the output of the eighth delay stage and all the remainingbasic and interpolated phase signals are supplied as respectivereference-clock phase signals PHASE0 to PHASE31. These 32reference-clock phase signals PHASE0 to PHASE31 are applied torespective inputs I0 to I31 of each of the first and second multiplexerelements 190 and 200. Each multiplexer element 190 and 200 also has aselection input S and an output Z. A first selection signal SEL1 outputby the DPLL circuit 180 is applied to the selection input S of the firstmultiplexer element 190. The first selection signal SEL1 is also appliedto one input of the adder 220. The other input of the adder 220 isconnected to receive a user-programmable offset signal OFFSET. A secondselection signal SEL2 output by the adder 220 is applied to theselection input S of the second multiplexer element 200.

[0154] The output Z of the first multiplexer element 190 is connected toa first input of a phase detector 182 of the DPLL circuit 180. Arecovered clock signal RCVCLK is produced at the Z output of the firstmultiplexer element 190.

[0155] An incoming serial data stream DIN is applied to a second inputof the phase detector 182. The phase detector 182 determines whether thetransitions in the incoming data stream DIN are ahead of, or behind, thetransitions in the recovered clock signal RCVCLK. Based on thedetermination the phase detector 182 produces either an advance controlsignal ADV or a retard control signal RET. The control signals ADV andRET are applied to a loop filter 184 which controls the effectivebandwidth of a phase lock loop provided by the DPLL circuit 180.

[0156] The DPLL circuit 180 may be a digital implementation of a singlepole, single zero second-order loop. In this case, the loop filter 184may provide a user-programmable and/or dynamically-variable low-passfilter function. For example, the loop bandwidth may be varieddynamically under digital control to achieve rapid acquisition of datawhen out of lock (wide bandwidth, wide capture range) and high rejectionof jitter when in lock (narrow bandwidth, narrow lock range).

[0157] In dependence upon the ADV and RET control signals the loopfilter 184 produces a control signal CS which is applied to a selectioncontroller 186. The selection controller 186 produces theabove-mentioned first selection signal SEL1 based on the control signalCS.

[0158] The first multiplexer element 190 selects one of the 32 clockphases PHASE0 to PHASE31 according to the first selection signal SEL1and outputs the selected clock phase as the recovered clock signalRCVCLK.

[0159] The DPLL circuit 180 causes each new selection of the clock phasePHASE0 to PHASE31 to be made in dependence upon a phase differenceand/or frequency difference between the incoming serial data stream DINand the presently-selected clock phase RCVCLK. The feedback loopprovided by the DPLL circuit 180 serves to tend to select, as therecovered clock signal RCVCLK, that one of the clock phases PHASE0 toPHASE31 which at any given time differs least in phase from the serialdata stream DIN. When the first selection signal SEL1 reaches itsmaximum value, corresponding to PHASE31 at one end of the delay line172, it changes to the minimum value, effectively wrapping around toPHASE0 at the other end of the delay line 172. Thus, there is no phasejump in going from one end of the delay line to the other. This isbecause a jump back from phase 31 to phase 0 is indistinguishable from ajump forward of just one phase. In addition, the first selection signalSEL1 is preferably a Gray-coded signal so that unnecessary phase jumpsdo not occur when changing the value of the selection signal SEL1.

[0160] The adder 220 adds together the respective values of the SEL1 andOFFSET signals to produce the SEL2 signal. The adder 220 is a modulo-32adder in this embodiment. The value of the OFFSET signal can be positiveor negative. The SEL2 signal is also preferably a Gray-coded signal.

[0161] In accordance with the value of the SEL2 signal the secondmultiplexer element 200 selects one of the clock phases PHASE0 toPHASE31 as the offset clock signal OFFCLK. The serial data stream DIN istherefore latched by the data latch 210 at each rising edge of theoffset clock signal OFFCLK.

[0162] Because the offset clock signal OFFSET is user-programmable thephase of the offset clock signal OFFCLK can be chosen by the user tosuit the particular shape of the data eye in the data stream DIN. Theoffset clock signal OFFCLK can be advanced or retarded relative to thatof the recovered clock signal RCVCLK, giving greater flexibility.Furthermore, the phase of the offset clock signal OFFCLK relative tothat of the recovered clock signal RCVCLK is controlled accuratelyirrespective of PVT variation in the data recovery circuitry 160.

What we claim is:
 1. Signal generating circuitry comprising: a firstclocked element connected for receiving a clock signal and a firstsynchronised signal which changes its logic state synchronously withrespect to said clock signal, and switchable by said clock signalbetween a responsive state, in which the element is operable in responseto said state change in said first synchronised signal to change a logicstate of a second synchronised signal produced thereby, and anon-responsive state in which no state change in the second synchronisedsignal occurs; and a second clocked element connected for receiving saidclock signal and said second synchronised signal, and switchable by saidclock signal between a responsive state, in which the element isoperable in response to said state change in said second synchronisedsignal to change a logic state of a third synchronised signal producedthereby, and a non-responsive state in which no state change in thethird synchronised signal occurs; wherein, when said clock signal has afirst logic state the first clocked element has said non-responsivestate and said second clocked element has said responsive state, andwhen said clock signal has a second logic state the first clockedelement has said responsive state and said second clocked element hassaid non-responsive state.
 2. Circuitry as claimed in claim 1, whereinthe clock signal has alternate first and second clock edges and changesat each first clock edge from said second logic state to said firstlogic state and changes at each second clock edge from said first logicstate to said second logic state, and a switching time of said firstclocked element is less than an interval between each second clock edgeand the following first clock edge, and a switching time of said secondclocked element is less than an interval between each first clock edgeand its following second clock edge.
 3. Circuitry as claimed in claim 1,wherein each of said first and second clocked elements is a transparentor half latch element.
 4. Circuitry as claimed in claim 1, wherein saidstate change in said first synchronising signal is permitted to occurbetween a first clock edge and its following second clock edge orbetween a second clock edge and its following first clock edge. 5.Circuitry as claimed in claim 1, further comprising an input circuitconnected for receiving said clock signal and an input signal that ispermitted to change its logic state asynchronously with respect to saidclock signal and operable, following the said state change in the inputsignal, to bring about the said state change in said first synchronisedsignal synchronously with respect to said clock signal.
 6. Circuitry asclaimed in claim 5, wherein said first synchronised signal is producedby a further clocked element in said input circuit, and a switching timeof said further clocked element is greater than that of each of saidfirst and second clocked elements.
 7. Circuitry as claimed in claim 6,wherein the switching time of said further clocked element is permittedto be greater than one or each of the said intervals.
 8. Circuitry asclaimed in claim 6, wherein said further clocked element is amaster/slave or full latch element.
 9. Circuitry as claimed in claim 6,wherein said further clocked element has a reset input to which saidinput signal is applied, a data input to which a signal having apredetermined logic state is applied, and a data output at which saidfirst synchronised signal is produced, whereby said state change in saidfirst synchronised signal occurs after said further clocked element isreleased from a reset condition by said state change in said inputsignal.
 10. Circuitry as claimed in claim 1, further comprising a thirdclocked element connected for receiving said clock signal and said thirdsynchronised signal, and switchable by said clock signal between aresponsive state, in which the element is operable in response to saidstate change in said third synchronised signal to change a logic stateof a fourth synchronised signal produced thereby, and a non-responsivestate in which no state change in the fourth synchronised signal occurs;said third clocked element having said responsive state when said clocksignal has said second logic state and having said non-responsive statewhen said clock signal has said first logic state.
 11. Clock recoverycircuitry, operable to perform a repeating series of N cycles, whereN≧2, comprising: N rising-edge latches, each connected for receiving astream of serial data and each triggered at a rising edge of a differentone of the N cycles of said repeating series to take a rising-edgesample of the data; N falling-edge latches, each connected for receivingthe data stream and each triggered at a falling edge of a different oneof the N cycles of said repeating series to take a falling-edge sampleof the data; and a sample processing circuit which processes the samplesto recover a clock signal from the data stream.
 12. Circuitry as claimedin claim 11, having: a controller which generates N first synchronisedsignals, each said first synchronised signal having an active state foran individually corresponding one of the N cycles of the said repeatingseries and having an inactive state in each non-corresponding cycle ofthe series; and N processing circuits, each comprising: an input forreceiving a different one of said N first synchronised signals; a firstclocked element connected for receiving a clock signal and said onefirst synchronised signal, and switchable by said clock signal between aresponsive state, in which the element is operable in response to saidstate change in said first synchronised signal to change a logic stateof a second synchronised signal produced thereby, and a non-responsivestate in which no state change in the second synchronised signal occurs;a second clocked element connected for receiving said clock signal andsaid second synchronised signal, and switchable by said clock signalbetween a responsive state, in which the element is operable in responseto said state change in said second synchronised signal to change alogic state of a third synchronised signal produced thereby, and anon-responsive state in which no state change in the third synchronisedsignal occurs; a third clocked element connected for receiving saidclock signal and said third synchronised signal, and switchable by saidclock signal between a responsive state, in which the element isoperable in response to said state change in said third synchronisedsignal to change a logic state of a fourth synchronised signal producedthereby, and a non-responsive state in which no state change in thefourth synchronised signal occurs; wherein, when said clock signal has afirst logic state the first and third clocked elements have saidnon-responsive state and said second clocked element has said responsivestate, and when said clock signal has a second logic state the first andthird clocked elements have said responsive state and said secondclocked element has said non-responsive state; and each of said Nprocessing circuits further comprising: one of said rising-edge latchesconnected to be enabled by one of said third and fourth synchronisedsignals; and one of said falling-edge latches connected to the enabledby the other of said third and fourth synchronised signals. 13.Circuitry as claimed in claim 12, wherein the said controller comprisesa circulating control register having N storage elements, each forstoring one bit of an N-bit control pattern that is transferred incircular manner through the register, one bit of the said controlpattern having a first value and each other bit having a second value,and each storage element providing one of the said output signals, whichoutput signal has said active state when the bit of the control patternstored in the storage element has said first value and which has saidinactive state when that stored bit has said second value.
 14. Circuitryas claimed in claim 13 wherein each said storage element comprises anedge-triggered latch element which produces the said output signal. 15.Verification circuitry, for connection to a circulating control registerto verify that a predetermined N-bit control pattern is circulatingcorrectly through the register, the register having N storage elements,each for storing one bit of the control pattern, and one bit of thecontrol pattern having a first value and each other bit having a secondvalue, the verification circuitry comprising: a first check circuit,connected operatively to a first set of two or more consecutive storageelements of the register, and producing a first check signal which has afirst state when any of the storage elements of the first set has saidfirst value and which has a second state when all of the storageelements of the first set have said second value; a second checkcircuit, connected operatively to the remaining storage elements of theregister which form a second set of two or more consecutive storageelements, and producing a second check signal which has a first statewhen any of the storage elements of the second set has said first valueand which has a second state when all of the storage elements of thesecond set have said second value; and a same state detection circuitconnected to said first and second check circuits and producing adetection signal, indicating that said control pattern is incorrect,when said first and second check signals have the same state. 16.Circuitry as claimed in claim 15, wherein said first value is a zero andsaid second value is a one, and each said check circuit performs an ANDor NAND operation on the respective stored values of the storageelements of its set.
 17. Circuitry as claimed in claim 15, wherein thesaid first value is a one and said second value is a zero, and each saidcheck circuit performs an OR or NOR operation on the respective storedvalues of the storage elements of its set.
 18. Circuitry as claimed inclaim 15, wherein said same state detection circuit operates to producesaid detection signal at a predetermined detection time following acirculation operation of the control register when the states of thefirst and second check signals have stabilised.
 19. Data synchronisingcircuitry, for receiving successively first items of data and foroutputting successively second items of data derived from the receivedfirst items, one of said first items being received in each cycle of afirst clock signal and one of said second items being output in eachcycle of a second clock signal having a frequency N times that of thefirst clock signal, where N is an integer, which circuitry comprises: areset signal generator which causes a reset signal to be changed from anactive state to an inactive state at a preselected point in afirst-clock-signal cycle; a counter connected for receiving said secondclock signal and said reset signal and operable, following the change ofsaid reset signal to said inactive state, to count pulses of said secondclock signal and to produce transfer control signals at intervals of Ncycles of said second clock signal; and a data converter connected forreceiving said transfer control signals and said second clock signal,and operable to accept respective first items in response to successivesaid transfer control signals and to derive said second items from thereceived first items and to output one of said second items persecond-clock-signal cycle.
 20. Circuitry as claimed in claim 19, whereinsaid first items of data each have N bits and said second items of dataeach have a single bit.
 21. Circuitry as claimed in claim 19, whereinsaid data converter is a parallel-to-serial converter.
 22. Circuitry asclaimed in claim 19, wherein: said counter comprises a circulatingcontrol register having N storage elements, each for storing one bit ofan N-bit control pattern that is transferred in circular manner throughthe register in successive second-clock-signal cycles, one bit of saidcontrol pattern having a first value and each other bit having a secondvalue; and one of said transfer control signals is produced each timethe bit of the control pattern stored in a predetermined one of thestorage elements has said first value.
 23. Circuitry as claimed in claim19, wherein said reset signal generator is connected for receiving bothsaid first and said second clock signals and is operable to detect apreselected change in logic state of said first clock signal and, inresponse to such detection, to bring about said change of said resetsignal from said active state to said inactive state in synchronism withsaid second clock signal.
 24. Circuitry as claimed in claim 19, whereinsaid reset signal generator comprises: a first synchronising circuitconnected for receiving said first clock signal and an input signal thatis permitted to change its logic state asynchronously with respect tosaid first clock signal, and operable, following the said state changein the input signal, to bring about a change in logic state of adetection signal; and a second synchronising circuit connected forreceiving said second clock signal and said detection signal andoperable, following said state change in said detection signal, to bringabout the said change of said reset signal from said active state tosaid inactive state in synchronism with said second clock signal. 25.Circuitry as claimed in claim 24, wherein said first synchronisingcircuit comprises a clocked element having a clock input to which saidfirst clock signal is applied, a reset input to which said input signalis applied, a data input to which a signal having a predetermined logicstate is applied, and a data output from which said detection signal isderived, whereby said state change in said detection signal occurs aftersaid clocked element of said first synchronising circuit is releasedfrom a reset condition by said state change in said input signal. 26.Circuitry as claimed in claim 24, wherein said second synchronisingcircuit comprises a clocked element having a clock input to which saidsecond clock signal is applied, a reset input to which said input signalis applied, a data input to which said detection signal is applied, anda data output from which said reset signal is derived, whereby saidstate change in said reset signal occurs after said clocked element ofsaid second synchronising circuit is released from a reset condition bysaid state change in said input signal and after said state change insaid detection signal.
 27. Data recovery circuitry, for sampling areceived serial data stream, comprising: a clock recovery circuitconnected for receiving a plurality of candidate clock signals havingthe same frequency but spaced apart one from the next in phase, andoperable to select, as a recovered clock signal, one of said candidateclock signals that matches said received serial data stream in phase; anoffset clock circuit operable to select, as an offset clock signal, afurther one of said candidate clock signals different from saidcandidate clock signal selected as said recovered clock signal; and adata sampling circuit operable to sample said received data stream usingsaid offset clock signal.
 28. Circuitry as claimed in claim 27, whereinsaid offset clock circuit is operable to select, as said offset clocksignal, one of said candidate clock signals that leads said recoveredclock signal in phase.
 29. Circuitry as claimed in claim 27, whereinsaid offset clock circuit is connected for receiving an offset clocksignal and is operable to select said further one of said candidateclock signals in dependence upon the received offset clock signal. 30.Circuitry as claimed in claim 29, wherein said offset control signal isa user-adjustable control signal.
 31. Circuitry as claimed in claim 29,wherein said clock recovery circuit generates a first selection signalfor designating the candidate clock signal selected as said recoveredclock signal, and said offset clock circuit generates a second selectionsignal, for designating the said further candidate clock signal selectedas said offset clock signal, based on said first selection signal andsaid offset control signal.
 32. Circuitry as claimed in claim 31,wherein one or each of said first and second selection signals is aGray-coded signal.
 33. Circuitry as claimed in claim 31, wherein saidoffset clock circuit comprises a modulo-N adder which adds said offsetcontrol signal to said first selection signal to produce said secondselection signal, where N is the number of candidate clock signals inthe said plurality.
 34. Circuitry as claimed in claim 27, wherein amaximum absolute phase difference between any two of said candidateclock signals of said plurality is 180°.
 35. Circuitry as claimed inclaim 27, wherein said candidate clock signals of said plurality arespaced substantially equally in phase one from the next.
 36. Circuitryas claimed in claim 35, wherein a last one of the candidate clocksignals of said plurality differs in phase from a first one of saidcandidate clock signals of said plurality by substantially the sameamount as the two candidate clock signals of each further pair ofmutually-adjacent candidate clock signals of said plurality differ inphase from one another.
 37. Circuitry as claimed in claim 27, furthercomprising a multiphase clock signal generator including: a delay line,connected for receiving a reference clock signal having a frequencyequal or close to a data rate of said serial data stream and having aseries of individual delay stages from which said candidate clocksignals are derived; and a delay adjustment circuit which controls atotal delay imposed by the delay stages of said series to besubstantially equal to a duration of one cycle of said reference clocksignal.
 38. Circuitry as claimed in claim 37, wherein said delayadjustment circuit receives a first phase comparison signal applied toan input of a first one of the delay stages of said series, and a secondphase comparison signal produced at an output of a last one of the delaystages of said series, and is operable to control the said total delayso that said first and second phase comparison signals are maintained atsubstantially the same frequency but with transitions in said secondphase comparison signal being substantially aligned with correspondingtransitions in said first phase comparison signal.
 39. Circuitry asclaimed in claim 37, wherein the delay stages of said series are fewerin number than said candidate clock signals of said plurality, and saidmultiphase clock signal generator further includes a phase interpolatorconnected for receiving a plurality of basic phase signals produced bythe delay stages of said series and operable to produce a plurality ofinterpolated phase signals having phases intermediate between therespective phases of the basic phase signals.
 40. Circuitry as claimedin claim 27, wherein said clock recovery circuit compares the respectivephases of said received serial data stream and the candidate clocksignal currently selected as said recovered clock signal, and selects anext candidate clock signal from amongst the candidate clock signals ofsaid plurality based on the comparison results.
 41. Circuitry as claimedin claim 27, wherein said clock recovery circuit comprises a digitalphase lock loop circuit.
 42. Clock recovery circuitry as claimed inclaim 13, further comprising verification circuitry connected to saidcirculating control register of said controller for verifying that saidcontrol pattern is circulating correctly therethrough, the verificationcircuitry comprising: a first check circuit, connected operatively to afirst set of two or more consecutive storage elements of the register,and producing a first check signal which has a first state when any ofthe storage elements of the first set has said first value and which hasa second state when all of the storage elements of the first set havesaid second value; a second check circuit, connected operatively to theremaining storage elements of the register which form a second set oftwo or more consecutive storage elements, and producing a second checksignal which has a first state when any of the storage elements of thesecond set has said first value and which has a second state when all ofthe storage elements of the second set have said second value; and asame state detection circuit connected to said first and second checkcircuits and producing a detection signal, indicating that said controlpattern is incorrect, when said first and second check signals have thesame state.
 43. Data synchronising circuitry as claimed in claim 22,further comprising verification circuitry connected to said circulatingcontrol register of said counter for verifying that said control patternis circulating correctly therethrough, the verification circuitrycomprising: a first check circuit, connected operatively to a first setof two or more consecutive storage elements of the register, andproducing a first check signal which has a first state when any of thestorage elements of the first set has said first value and which has asecond state when all of the storage elements of the first set have saidsecond value; a second check circuit, connected operatively to theremaining storage elements of the register which form a second set oftwo or more consecutive storage elements, and producing a second checksignal which has a first state when any of the storage elements of thesecond set has said first value and which has a second state when all ofthe storage elements of the second set have said second value; and asame state detection circuit connected to said first and second checkcircuits and producing a detection signal, indicating that said controlpattern is incorrect, when said first and second check signals have thesame state.
 44. Verification circuitry, for connection to a circulatingcontrol register to verify that a predetermined N-bit control pattern iscirculating correctly through the register, the register having Nstorage elements, each for storing one bit of the control pattern, andone bit of the control pattern having a first value and each other bithaving a second value, the verification circuitry comprising: firstcheck means, connected operatively to a first set of two or moreconsecutive storage elements of the register, for producing a firstcheck signal which has a first state when any of the storage elements ofthe first set has said first value and which has a second state when allof the storage elements of the first set have said second value; secondcheck means, connected operatively to the remaining storage elements ofthe register which form a second set of two or more consecutive storageelements, for producing a second check signal which has a first statewhen any of the storage elements of the second set has said first valueand which has a second state when all of the storage elements of thesecond set have said second value; and same state detection meansconnected to said first and second check means for producing a detectionsignal, indicating that said control pattern is incorrect, when saidfirst and second check signals have the same state.